Electronic design automation (EDA) software systems commonly perform routing of networks (nets) of circuit designs, such as clock networks (hereafter, clock nets). Usually, net routing can be performed in two phases, where the first phase involves routing guides that attempt to generate timing-aware/timing-based global routing of nets, and the second phase involves detailed routing of nets with specific wires (e.g., metal traces) based on the routing guides, while attempting to resolve/avoid one or more design rule violations.
Global routing can comprise two-dimensional (2D) net routing, layer assignment of wires of nets, or track assignment of wires of nets. Resolving congestion and major design rule constraints (DRCs) during global routing can facilitate detailed routing of nets. Conventional global routing can route nets of a circuit design by dividing the circuit design (e.g., each layer of the circuit design) into a grid of cells (also referred to as “global routing cells” or “g-cells”), where each g-cell comprises a set number of resources (e.g., horizontal and vertical resources, such as tracks) for routing a net. Global routing can then route a net of the circuit design by assigning the net to a set of specific g-cells and a set of specific layers (metal layer) of the circuit design. Generally, using g-cells permits global routing to speed up the process of finding the net routing solutions by analyzing routing congestion based on g-cell congestion (e.g., a g-cell is considered congested if number of resources of the g-cell is less than what is needed to route a net through the g-cell) and by reducing the number of pathways to consider for net routing.
In some instances, conventional routing (e.g., conventional global routing) performs track assignment of wires based on panels (e.g., panel by panel), where each panel comprises a defined row of g-cells on one or more layers of the circuit design (e.g., metal layers M1, M2, M3, etc.) that fall within that defined row of g-cells. Traditionally, track assignment assigns a wire falling within a particular panel to a track within the same particular panel, and such a track assignment is determined independent of any wire track assignment within other (e.g., adjacent) panels. As such, traditional track assignment can not only cause wire overlap, but also cause DRCs to form based on wires or routing blockages that exist in different (e.g., neighboring) panels.